1. Field of the Invention
The present invention relates to a current comparator, and particularly to a current comparator with high speed and low current.
2. Description of Related Art
As the products with low voltage and low power consumption are entensively used, current comparators with low currents have always been concerned in the recent ten years. Besides, there is a trend to entensively utilize a current mode switching circuit instead of a voltage mode switching circuit. Therefore, the current comparator has become an important component. For example, a prior art in Journal of IEEE. Solid. State. Vol. 30, pp. 1239-1245, entitled xe2x80x9cA 200 MHz Pipelined Multiplier Using 1.5V-Supply Multiple-Valued MOS Current-Mode Circuits,xe2x80x9d disclosed an arithmetic operation of a current mode switching circuit. Besides, a current sense amplifier has been used to read data in a lot of SRAM, DRAM and Flash memory. For example, a reference is disclosed in Journal of IEEE. Solid. State. vol. 26, pp. 525-536, entitled xe2x80x9cCurrent-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM.xe2x80x9d Furtherrnore, the current mode switching circuit has also been used in an AID converter. For example, a prior art is disclosed in Electron Lett. Vol. 27, pp. 818-820, entitled xe2x80x9cCurrent-Mode Cyclic ADC for Low Power and High Speed Applications.xe2x80x9d In addition, some applications such as temperature sensor and image sensor, which are needed to generate a low current, also utilize a current comparator. A known problem called xe2x80x9cdead zonexe2x80x9d happens if the input current is so small that all transistors cannot be activated. Therefore, how to shrink the dead zone region of a current comparator is an important topic for engineers.
FIG. 1 is a prior art current comparator with positive feedback and low input impedance. When the current Iin flows into the circuit in FIG. 1 from the point V1, the output voltage Vout shows a high level voltage. On the contrary, when the current flows out of the circuit of FIG. 1, the output voltage Vout shows a low level voltage. If the amplitude of the input current is large enough, such as 10 xcexcA, the operational speed of the circuit is fast. But if the amplitude of the input current is so little, the operational speed will be greatly slowed down due to the existence of a dead zone.
To overcome the above problems, a fixed current method and a bias method that connects a pair of NMOS and PMOS transistors serving as diodes have been proposed. In the former method, a good and accurate current source is necessary. In the latter method, the substrate of the pair of NMOS and PMOS transistors needs to connect to source terminals, and that is difficult to implement in a CMOS technology. Besides, the latter method needs the two transistors having large channel widths to charge/discharge output terminals and thereby avoid a body effect if its source terminals do not connect to the substrate. In addition, the output terminal of the above prior art methods has to connect several inverters to output a rail-to-rail voltage since their driving capabilities are weak.
Another prior art method utilizes feedback resistors as shown in FIG. 2 to detect a low current. The disadvantage of the prior art is that its gain is not so large that a lot of inverters need to be cascaded to generate a rail-to-rail result.
In conclusion, known current comparators, especially when the current being under 1 xcexcA, have a complicated structure and a slow operational speed and consume too much power.
The primary object of the present invention is to offer a low current comparator having simple, cheap and fast characteristics, especially to provide a low current comparator having a small dead zone and an excellent driving capability.
For achieving the above objects, the present invention provides a current comparator with high speed and low current, which comprises a first CMOS transistor, a second CMOS transistor, a diode-configured N-type transistor, a third CMOS transistor, a fourth CMOS transistor and a fifth CMOS transistor. The first CMOS transistor includes a first P-type transistor and a first N-type transistor. Source terminals of the first P-type transistor and N-type transistor are connected to an input signal of the current comparator. The second CMOS transistor includes a second P-type transistor and a second N-type transistor. Gate terminals of the second P-type transistor and N-type transistor are connected to the input signal. The diode-configured N-type transistor has a gate-drain terminal and a source terminal, which are respectively connected to drain terminals of the second CMOS transistor. The gate-drain terminal of the diode-configured N-type transistor is further connected to the gate terminal of the first N-type transistor, and the source terminal of the diode-configured N-type transistor is further connected to the gate terminal of the first P-type transistor. The gate terminal of the N-type transistor of the third CMOS transistor is connected to the gate-drain terminal of the diode-configured N-type transistor, and the gate terminal of the P-type transistor of the third CMOS transistor is connected to the source terminal of the diode-configured N-type transistor. The gate terminals of the fourth CMOS transistor are connected to the output of the third CMOS transistor. The gate terminals of the fifth CMOS transistor are connected to the output of the fourth CMOS transistor, and the output of the fifth CMOS transistor is the output of the current comparator.
With the above structure, the diode-configured N-type transistor can also be replaced by a diode-configured P-type transistor, and just modifying a few connections. Since the gain of the first CMOS transistor increases and the input impedance of the first CMOS transistor decreases, the current comparator is sensitive to a low current and generates a fast response. In addition, since a diode-configured NMOS transistor pulling up the voltage of gate terminals of the input stage and output stage is used, the driving capability of the input stage and output stage of the present invention is enhanced and thereby the dead zone region is shrunk. Furthermore, since the gate-drain terminal and source terminal of the diode-configured NMOS are respectively connected to gate terminals of the third CMOS transistor, the driving capability of the fourth CMOS transistor will be enhanced and thereby avoid cascading a series of inverters shown in prior arts.
In another embodiment, MOS transistors whose gate terminals are applied with a modulated voltage and have the same carrier type with the transistors of the fourth CMOS transistor are connected to the drain terminals of the fourth CMOS transistor. Therefore, the present invention can adjust the switching voltage of the CMOS inverters according to different process corners.